
Silicon Packaging Engineer: End-to-End Substrate Design
Intel, Phoenix, AZ, United States
A leading semiconductor company in Phoenix, Arizona, is seeking a Silicon Packaging Engineer. The candidate will drive the development for mask and panel design, ensuring optimal layout and routing. Required qualifications include a Bachelor’s degree in electrical engineering and experience with design/layout tools like Valor and Cadence. The position offers competitive salary benefits, including health and retirement plans, and requires on-site presence at the Phoenix location.
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