FPGA Engineer Job at Indotronix International Corporation in Los Angeles County
Indotronix International Corporation, Los Angeles County, CA, United States
This position requires these skills and abilities: -RTL coding and simulation in VHDL or Verilog OR Testbench development for the verification of RTL blocks using UVM and SystemVerilog -Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure -Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synopsys, FPGA-specific tools) -Familiarity with revision control concepts and tools (e.g. Subversion) -Ability to work with minimal supervision, part of a team of engineers with a variety of skills and backgrounds -Strong oral and written communication skills and the ability to document and present one's work and status -Bachelor's Degree in applicable engineering field Key Responsibilities will include: -Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing analysis and closure, verification, and system integration -RTL coding and simulation in VHDL or Verilog -Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
In Summary: This position requires these skills and abilities: -RTL coding and simulation in VHDL or Verilog OR Testbench development for the verification of RTL blocks using UVM and SystemVerilog . - Ability to work with minimal supervision, part of a team of engineers with a variety of skills and backgrounds . -Strong oral and written communication skills and the ability to document and present one's work and status . -Bachelor's degree in applicable engineering field .
En Español: Este puesto requiere las siguientes habilidades y capacidades: -desarrollo de codificación y simulación RTL en VHDL o Verilog O Testbench para la verificación de bloques RTL utilizando UVM y SystemVerilog -Arquitectura de circuitos digitales, diseño, compensaciones de recursos, análisis del tiempo y cierre del tiempo-Proficiencia con herramientas ASIC y/o FPGA de simulación y síntesis (por ejemplo Modelsim, Synopsys, herramienta específica de FPG)
In Summary: This position requires these skills and abilities: -RTL coding and simulation in VHDL or Verilog OR Testbench development for the verification of RTL blocks using UVM and SystemVerilog . - Ability to work with minimal supervision, part of a team of engineers with a variety of skills and backgrounds . -Strong oral and written communication skills and the ability to document and present one's work and status . -Bachelor's degree in applicable engineering field .
En Español: Este puesto requiere las siguientes habilidades y capacidades: -desarrollo de codificación y simulación RTL en VHDL o Verilog O Testbench para la verificación de bloques RTL utilizando UVM y SystemVerilog -Arquitectura de circuitos digitales, diseño, compensaciones de recursos, análisis del tiempo y cierre del tiempo-Proficiencia con herramientas ASIC y/o FPGA de simulación y síntesis (por ejemplo Modelsim, Synopsys, herramienta específica de FPG)