DRAM Layout Engineer – Timing‑Driven Physical Design

A leading semiconductor company is seeking a Layout Engineer based in Boise, Idaho. In this role, you will develop high-quality physical designs for DRAM technologies, collaborating with global teams. Required skills include physical layout experience with EDA tools, knowledge of timing-driven workflows, and solid verification process knowledge. Benefits include extensive healthcare plans, paid time off, and support for personal growth. This position represents a chance to make significant contributions to innovative memory solutions.
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