Rivos Inc.
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Cache Microarchitecture & Logic Design
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Rivos Inc. Positions are open for full-time in the areas of Cache microarchitecture and logic design. Responsibilities: Own or participate in microarchitecture development and specification, from high-level exploration to detailed design. Develop, assess, and refine RTL designs to meet power, performance, area, and timing goals. Collaborate with multi-disciplinary teams to implement and validate physical design aspects such as timing, area, reliability, testability, and power. Support test bench development and simulation for functional and performance verification. Explore high-performance strategies and validate RTL design against targeted performance metrics. Requirements: 2+ years of experience in microprocessor or SOC design, with knowledge in: High-performance cache controllers, pipeline design, hazard detection, parity/ECC, coherency policies, replacement policies. Design of coherent on-chip fabrics and control structures. Proficiency in SystemVerilog. Experience with simulators and waveform debugging tools. Understanding of logic design principles, timing, and power implications. Knowledge of low power microarchitecture techniques. Understanding of high-performance CPU microarchitecture trade-offs. Programming experience in C or C++. Education and Experience:
PhD, Master’s, or Bachelor’s degree in a technical field. Seniority level:
Entry level Employment type:
Full-time Job function:
Design, Art/Creative, and Information Technology Industry:
Computer Hardware Manufacturing
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Cache Microarchitecture & Logic Design
role at
Rivos Inc. Positions are open for full-time in the areas of Cache microarchitecture and logic design. Responsibilities: Own or participate in microarchitecture development and specification, from high-level exploration to detailed design. Develop, assess, and refine RTL designs to meet power, performance, area, and timing goals. Collaborate with multi-disciplinary teams to implement and validate physical design aspects such as timing, area, reliability, testability, and power. Support test bench development and simulation for functional and performance verification. Explore high-performance strategies and validate RTL design against targeted performance metrics. Requirements: 2+ years of experience in microprocessor or SOC design, with knowledge in: High-performance cache controllers, pipeline design, hazard detection, parity/ECC, coherency policies, replacement policies. Design of coherent on-chip fabrics and control structures. Proficiency in SystemVerilog. Experience with simulators and waveform debugging tools. Understanding of logic design principles, timing, and power implications. Knowledge of low power microarchitecture techniques. Understanding of high-performance CPU microarchitecture trade-offs. Programming experience in C or C++. Education and Experience:
PhD, Master’s, or Bachelor’s degree in a technical field. Seniority level:
Entry level Employment type:
Full-time Job function:
Design, Art/Creative, and Information Technology Industry:
Computer Hardware Manufacturing
#J-18808-Ljbffr